Introduction to logic synthesis in FPGAs, followed by an overview of the implementation of algorithms in hardware, including the representation of data and signals.
| Paper title | Logic Synthesis |
|---|---|
| Paper code | ELEC444 |
| Subject | Electronics |
| EFTS | 0.0833 |
| Points | 10 points |
| Teaching period | Not offered in 2019 |
| Domestic Tuition Fees (NZD) | $653.49 |
| International Tuition Fees (NZD) | $2,757.23 |
- Limited to
- BSc(Hons), PGDipSci, MSc, MAppSc
- Contact
- tim.molteno@otago.ac.nz
- Teaching staff
- Dr Tim Molteno
- Textbooks
- Textbooks are not required for this paper.
- Graduate Attributes Emphasised
- Global perspective, Interdisciplinary perspective, Lifelong learning, Scholarship,
Critical thinking, Information literacy, Research, Self-motivation, Teamwork.
View more information about Otago's graduate attributes. - Learning Outcomes
- After completing this paper students are expected to:
- Have a working knowledge of modern logic synthesis techniques using the Verilog HDL
- Understand the techniques used to represent information in logic circuits
- Understand the benefits of implementing algorithms that process information in these circuits
- Use techniques for testing and validating the accuracy and performance of logic-based algorithms
