ELEC444 Logic Synthesis

Introduction to logic synthesis in FPGAs, followed by an overview of the implementation of algorithms in hardware, including the representation of data and signals.

Paper title	Logic Synthesis
Paper code	ELEC444
Subject	Electronics
EFTS	0.0833
Points	10 points
Teaching period	Not offered in 2019
Domestic Tuition Fees (NZD)	$653.49
International Tuition Fees (NZD)	$2,757.23

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Limited to

BSc(Hons), PGDipSci, MSc, MAppSc

Contact

tim.molteno@otago.ac.nz

Teaching staff

Dr Tim Molteno

Textbooks

Textbooks are not required for this paper.

Graduate Attributes Emphasised

Global perspective, Interdisciplinary perspective, Lifelong learning, Scholarship, Critical thinking, Information literacy, Research, Self-motivation, Teamwork.
View more information about Otago's graduate attributes.

Learning Outcomes

After completing this paper students are expected to:

1. Have a working knowledge of modern logic synthesis techniques using the Verilog HDL
2. Understand the techniques used to represent information in logic circuits
3. Understand the benefits of implementing algorithms that process information in these circuits
4. Use techniques for testing and validating the accuracy and performance of logic-based algorithms

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Introduction to logic synthesis in FPGAs, followed by an overview of the implementation of algorithms in hardware, including the representation of data and signals.

Paper title	Logic Synthesis
Paper code	ELEC444
Subject	Electronics
EFTS	0.0833
Points	10 points
Teaching period	Not offered in 2020
Domestic Tuition Fees (NZD)	$666.57
International Tuition Fees (NZD)	$2,895.09

^ Top of page

Limited to

BSc(Hons), PGDipSci, MSc, MAppSc

Contact

tim.molteno@otago.ac.nz

Teaching staff

Dr Tim Molteno

Textbooks

Textbooks are not required for this paper.

Graduate Attributes Emphasised

Global perspective, Interdisciplinary perspective, Lifelong learning, Scholarship, Critical thinking, Information literacy, Research, Self-motivation, Teamwork.
View more information about Otago's graduate attributes.

Learning Outcomes

After completing this paper students are expected to:

1. Have a working knowledge of modern logic synthesis techniques using the Verilog HDL
2. Understand the techniques used to represent information in logic circuits
3. Understand the benefits of implementing algorithms that process information in these circuits
4. Use techniques for testing and validating the accuracy and performance of logic-based algorithms

^ Top of page