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ELEC444 Logic Synthesis

NOT OFFERED IN 2018

Paper Description

Introduction to logic synthesis in FPGAs, followed by an overview of the implementation of algorithms in hardware, including the representation of data and signals.

Modern devices commonly use logic synthesis to enable sophisticated algorithms to be embedded inside application-specific circuits. This course introduces the techniques and tools that are used to implement these designs, both from a theoretical and a practical point-of-view.

Prerequisites:
ELEC 358

This paper consists of 12 lectures and 7 tutorials. There are 3 assignments.

Assesment:
Final Exam 70%, Assignments 30%

Important information about assessment for ELEC444

Course Coordinator:
Dr Tim Molteno

After completing this paper students are expected to have achieved the following major learning objectives:

  • have a working knowledge of modern logic synthesis techniques using the Verilog HDL
  • understand the techniques used to represent information in logic circuits
  • understand the benefits of implementing algorithms that process information in these circuits
  • use techniques for testing and validating the accuracy and performance of logic-based algorithms

Additional outcomes:
To provide students with the practical skills required to fabricate electronic devices in a range of applications using modern techniques.

Topics:

  • Introduction to Logic Synthesis, and hardware description languages
  • Verilog HDL, Number representations and efficiency
  • Discrete approximations
  • Representing algorithms in logic circuits
  • Tradeoffs in circuit complexity and size
  • Order of algorithms
  • Signal processing in hardware
  • Digital filters, finite-impulse response
  • Infinite impulse response filters
  • Solving ODEs in hardware (system modeling)
  • Testing and Verification

 


Formal University Information

The following information is from the University’s corporate web site.

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Details

Introduction to logic synthesis in FPGAs, followed by an overview of the implementation of algorithms in hardware, including the representation of data and signals.

Paper title Logic Synthesis
Paper code ELEC444
Subject Electronics
EFTS 0.0833
Points 10 points
Teaching period Not offered in 2019
Domestic Tuition Fees (NZD) $653.49
International Tuition Fees (NZD) $2,757.23

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Limited to
BSc(Hons), PGDipSci, MSc, MAppSc
Contact
tim.molteno@otago.ac.nz
Teaching staff
Dr Tim Molteno
Textbooks
Textbooks are not required for this paper.
Graduate Attributes Emphasised
Global perspective, Interdisciplinary perspective, Lifelong learning, Scholarship, Critical thinking, Information literacy, Research, Self-motivation, Teamwork.
View more information about Otago's graduate attributes.
Learning Outcomes
After completing this paper students are expected to:
  1. Have a working knowledge of modern logic synthesis techniques using the Verilog HDL
  2. Understand the techniques used to represent information in logic circuits
  3. Understand the benefits of implementing algorithms that process information in these circuits
  4. Use techniques for testing and validating the accuracy and performance of logic-based algorithms

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Timetable

Not offered in 2019

Location
Dunedin
Teaching method
This paper is taught On Campus
Learning management system
None

Introduction to logic synthesis in FPGAs, followed by an overview of the implementation of algorithms in hardware, including the representation of data and signals.

Paper title Logic Synthesis
Paper code ELEC444
Subject Electronics
EFTS 0.0833
Points 10 points
Teaching period Not offered in 2020
Domestic Tuition Fees Tuition Fees for 2020 have not yet been set
International Tuition Fees Tuition Fees for international students are elsewhere on this website.

^ Top of page

Limited to
BSc(Hons), PGDipSci, MSc, MAppSc
Contact
tim.molteno@otago.ac.nz
Teaching staff
Dr Tim Molteno
Textbooks
Textbooks are not required for this paper.
Graduate Attributes Emphasised
Global perspective, Interdisciplinary perspective, Lifelong learning, Scholarship, Critical thinking, Information literacy, Research, Self-motivation, Teamwork.
View more information about Otago's graduate attributes.
Learning Outcomes
After completing this paper students are expected to:
  1. Have a working knowledge of modern logic synthesis techniques using the Verilog HDL
  2. Understand the techniques used to represent information in logic circuits
  3. Understand the benefits of implementing algorithms that process information in these circuits
  4. Use techniques for testing and validating the accuracy and performance of logic-based algorithms

^ Top of page

Timetable

Not offered in 2020

Location
Dunedin
Teaching method
This paper is taught On Campus
Learning management system
None