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ELEC358 Digital Electronic Design

Paper Description

This paper introduces digital electronics, and two aspects of electronic design automation. The first is computer interfacing and circuit design using modern CAD tools. The second is an intensive introduction to programmable logic, and the Verilog hardware description language.

Modern electronic design makes extensive use of programmable logic. Hardware Description Languages (HDLs), combined with Complex Programmable Logic Devices (CPLD's) and Field Programmable Gate Arrays (FPGA's) allow us to design and develop very complex systems including CPU's and entire systems on a single chip. You will learn how to use the Verilog HDL to synthesize and simulate complex circuits.

The paper is taught in two parts: 8 lectures on digital electronics, and 16 lectures on FPGAs and applications. There are two lectures per week, and one four-hour lab each fortnight. The second part of the course is intensively lab-based, and the weekly lectures are taught in the lab setting.

Assessment:
Final exam 40%, Assignments 24%, Laboratories 36%

Important information about assessment for ELEC358

Course Coordinator:
Dr Tim Molteno

After completing this paper students will be able to:
  1. Interpret typical code structures provided in a hardware description language
  2. Model, analyse, simulate and design the schematics of simple digital electronic circuits
  3. Recognise different latches, flip-flops and bistable elements
  4. Implement simple combinational circuits (eg buses, comparators, arithmetic-logic units)
  5. Understand sequential circuits (eg counters and shift registers) and use them in simple projects
  6. Advance their skills in identifying, formulating and solving digital-electronics problems

Lecture Topics

TopicLecturer: Dr Tim Molteno
Digital logic circuits
Circuit simulations
Printed circuit board design
Computer interfacing
Field-Programmable Gate Arrays
Introduction to Verilog hardware description language

 


Formal University Information

The following information is from the University’s corporate web site.

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Details

Digital logic circuits. Circuit simulations. Printed circuit board design. Computer interfacing. Field-programmable Gate Arrays including an introduction to the Verilog hardware description language.

This paper provides the student with the theoretical and practical skills required for the analysis, computer simulation and design of basic digital integrated circuits. The paper is an introduction to the study of Very Large Scale Integrated (VLSI) digital circuits. In particular, this paper emphasises the standard design flow consisting of hardware description, simulation and synthesis using the Verilog language for combinational and sequential logic circuits and systems.

Paper title Digital Electronic Design
Paper code ELEC358
Subject Electronics
EFTS 0.1500
Points 18 points
Teaching period Second Semester
Domestic Tuition Fees (NZD) $1,200.45
International Tuition Fees (NZD) $4,492.80

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Prerequisite
ELEC 353
Recommended Preparation
COMP 150 or COMP 160
Schedule C
Science
Contact
tim@physics.otago.ac.nz
Teaching staff
Course co-ordinator: Dr Tim Molteno
Textbooks
Text books are not required for this paper.
Graduate Attributes Emphasised
Global perspective, Interdisciplinary perspective, Lifelong learning, Scholarship, Communication, Critical thinking, Information literacy, Self-motivation, Teamwork.
View more information about Otago's graduate attributes.
Learning Outcomes
By the end of the module students are expected to be able to:
  1. Interpret typical code structures provided in a hardware description language
  2. Model, analyse, simulate and design the schematics of simple digital electronic circuits
  3. Recognise different latches, flip-flops and bistable elements
  4. Implement simple combinational circuits (eg buses, comparators, arithmetic-logic units)
  5. Understand sequential circuits (eg counters and shift registers) and use them in simple projects
  6. Advance their skills in identifying, formulating and solving digital-electronics problems

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Timetable

Second Semester

Location
Dunedin
Teaching method
This paper is taught On Campus
Learning management system
None

Lecture

Stream Days Times Weeks
Attend
L1 Monday 11:00-11:50 28-34, 36-41
Friday 11:00-11:50 28-34, 36-41

Practical

Stream Days Times Weeks
Attend
P1 Wednesday 14:00-17:50 29, 31, 33, 36, 38, 40